Details
System-level Test and Validation of Hardware/Software Systems
Springer Series in Advanced Microelectronics, Band 17
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96,29 € |
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| Verlag: | Springer |
| Format: | |
| Veröffentl.: | 30.03.2006 |
| ISBN/EAN: | 9781846281457 |
| Sprache: | englisch |
| Anzahl Seiten: | 180 |
Dieses eBook enthält ein Wasserzeichen.
Beschreibungen
<P>New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.</P>
<P>SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.</P>
<P>This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:</P>
<UL>
<LI>modeling of bugs and defects;</LI>
<LI>stimulus generation for validation and test purposes (including timing errors;</LI>
<LI>design for testability.</LI></UL>
<P>SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.</P>
<P>This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:</P>
<UL>
<LI>modeling of bugs and defects;</LI>
<LI>stimulus generation for validation and test purposes (including timing errors;</LI>
<LI>design for testability.</LI></UL>
Modeling Permanent Faults.- Test Generation: A Symbolic Approach.- Test Generation: A Heuristic Approach.- Test Generation: A Hierarchical Approach.- Test Program Generation from High-level Microprocessor Descriptions.- Tackling Concurrency and Timing Problems.- An Approach to System-level Design for Test.- System-level Dependability Analysis.
<P>Matteo Sonza Reorda is the leader of the computer-aided design group of the Dipartimento di Automatica e Informatica, Politecnico di Torino. Zebo Peng is Professor of the chair in Computer Systems and Director of the Embedded Systems Laboratory at Linköping University.</P>
<P>New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.</P>
<P>As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.</P>
<P><EM>System-level Test and Validation of Hardware/Software Systems</EM> provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:</P>
<P>• modeling of bugs and defects;</P>
<P>• stimulus generation for validation and test purposes (including timing errors;</P>
<P>• design for testability.</P>
<P>For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, <EM>System-level Test and Validation of Hardware/Software Systems</EM> will be an invaluable source of reference.</P>
<P>As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.</P>
<P><EM>System-level Test and Validation of Hardware/Software Systems</EM> provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:</P>
<P>• modeling of bugs and defects;</P>
<P>• stimulus generation for validation and test purposes (including timing errors;</P>
<P>• design for testability.</P>
<P>For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, <EM>System-level Test and Validation of Hardware/Software Systems</EM> will be an invaluable source of reference.</P>
The reader will learn about the state of the art in system-level validation and test procedures which will enhance both the reliability and performance of system on chip designs
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