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<p>Chapter 1. Introduction.- Chapter 2. FinFET Technology.- Chapter 3. Reliability Challenges in FinFETs.- Chapter 4. Circuit-Level Mitigation Approaches.- Chapter 5. Evaluation Methodology.- Chapter 6. Process Variability Mitigation.- Chapter 7. Soft Error Mitigation.- Chapter 8. General Trade-offs.- Chapter 9. Final Remarks.</p>

Alexandra Zimpeck received the Computer Engineering degree from the Federal University of Rio Grande (FURG), Rio Grande, Brazil, in 2013, and the Master degree in Computer Science, option Microelectronics from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 2016. She received the Ph.D. degree in Computer Science, option Microelectronics from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, and also the Ph.D. degree in Micro and Nano Systems from Toulouse University, Toulouse, France, 2019. She has been a Professor with the Catholic University of Pelotas (UCPel) since 2020. She was a researcher at ONERA, The French Aerospace Lab, Toulouse, France. She develops research in the areas of microelectronics, nanotechnology, and embedded systems, focusing mainly on the reliability topics such as the investigation and mitigation of process variability effects and radiation-induced soft errors in emergent technologies. She has authored and co-authored more than 40 papers in journals, conference proceedings, and book chapters. <p></p>

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<p>Cristina Meinhardt is Adjunct Professor at Federal University of Santa Catarina - UFSC.&nbsp; She holds a degree in Computer Engineering from the Federal University of Rio Grande (FURG), a Master's and a PhD in Computer Science from the Federal University of Rio Grande do Sul (UFRGS).&nbsp; She develops research in the areas of computational systems architectures, microelectronics, nanotechnology, embedded systems and development of EDA tools, with the main focus in the area of mitigation of the effects of variability and radiation faults. She is a Senior Member of IEEE and member of IEEE CASS, SBC and SBMicro.</p>

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Laurent Artola (MSEE 2007, Ph.D. EE 2011) is a research engineer at ONERA since 2012. His researches are focus on radiations effects in devices and integrated circuits, modeling and characterization of Single Event Effects and total ionization dose.He received the best ONERA physics PhD award and the best PhD presentation award. He is regularly involved in radiations R&D projects for space applications. He has served the radiation effects and microelectronics reliability communities as reviewers, session chairman, and member of the award comity for the IEEE Nuclear and Space Radiation Effects Conference (NSREC) and Space Radiation Effects in Components and Systems (RADECS) European conference. Laurent serves as reviewers in more than ten journals. He has authored and co-authored more than 30 papers, including one best paper award at RADECS conference paper. <p></p>

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Ricardo Reis (M’81–SM’06) received the Electrical Engineering degree from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and the Ph.D. degree in informatics, option microelectronics from the Institut National Polytechnique de Grenoble, Grenoble, France, in 1983. He received the Doctor Honoris Causa from University ofMontpellier, France, in 2016. He has been a Full Professor with UFRGS since 1981. He is at research level 1A of the CNPq (Brazilian National Science Foundation), Brasília, Brazil, and the Head of several research projects supported by government agencies and industry. He has published over 600 papers in journals and conference proceedings and authored or co-authored several books. His current research interests include physical design, physical design automation, design methodologies, digital design, EDA, circuits tolerant to radiation, and microelectronics education. Prof. Reis was a recipient of the IEEE Circuits and Systems Society (CASS) Meritorious Service Award 2015. He was the Vice President of the IEEE CASS representing Region 9 (Latin America) and Brazilian Computer Society (SBC). He is the Chair of IFIP TC10. He has also organized several international conferences. He was a member of the CASS Distinguished Lecturer Program 2014–2015. He is member of the IEEE CASS BoG (2018-2020). <p></p>

This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. &nbsp;The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.<div><p><ul><li>Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells;</li><li>Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments;</li><li>Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors;</li><li>Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features;</li><li>Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.</li></ul></p></div>

Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations